Low - Power Architectural Design Methodologies

Low-Power Architectural Design Methodologies by Paul Eric Landman Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California at Berkeley Professor Jan M. Rabaey, Chair In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, battery-operated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom and complexity to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support low-power system design. Low-power techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the register-transfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switch-level accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis. Jan M. Rabaey Committee Chairman 1 Jan M. Rabaey